System Verilog Function return value as parameterized bit vector -

i need create function in system verilog return value parameterized bit vector. code follows:

class my_class #(parameter addr_width = 32);     bit [addr_width-1:0] address;      function bit [addr_width-1:0] get_address();         return address;     endfunction : get_address  endclass : my_class 

i compile time error in function declaration saying parameter addr_width not defined. can please explain why happening? same working without parameter (i.e if have known value bit [31:0])

there nothing wrong code showed in original example, , i've tried on earlier versions of questa. when unexplainable errors on code looks fine, either using version old, or real error on line above the code in question.