verilog - How can I set a full variable constant? -

when number size variable , must set parameter, how can set maximum number? in following, result must "ffff", simulator returns "f". fix problem?

`define size 10 module tb1;     reg [15:0] a;      initial begin         = `size'hf;         $display("a=%h",a);     end endmodule

you can use replication operator construct bit vectors.

{a{b}} produces vector a copies of vector b.

in case be:

 = {`size{1'b1}};

Sher